1. Field of the Invention
The present invention relates to a packet synchronization detector according to the preamble of claim 1 and to a method to determine the lock-in to a regularly repeated predetermined synchronization pattern within an incoming digital signal according to the preamble of claim 7.
2. Description of Related Art including information disclosed under 37 CFR 1.97 and 1.98
In general a synchronization pattern, e. g. a synchronization byte, is included in a transmitted bit stream to allow a synchronization of the receiver to this bit stream, i. e. to find byte boundaries and the boundaries of transmission packets or frames. E. g., in integrated DVB channel decoders, a stream of 2, 4, 5, 6, 7 or 8 bit symbols must be converted to a stream of bytes. Therefore, the stream of bit symbols gets first converted to a stream of bits whereafter the byte boundaries are detected on basis of a transmitted synchronization byte which always has the value 0xc3x9747 or the respective inversion 0xc3x97b8 and is transmitted every 204 bytes, since DVB transmissions always use the MPEG transport packet structure which uses a fixed packet size of 204 bytes.
Current packet synchronization detectors use a single pattern detector that detects the synchronization byte value in the serial bit stream. If such a pattern has been found the patterns nxc2x7204 bytes later are checked and a lock-in of the receiver is achieved if these are also synchronization bytes.
The disadvantage of this solution is that there is a high probability that the first matching pattern is not a synchronization byte. In this case there is a penalty time of at least one packet until the search can continue.
Therefore, it is the object of the present invention to provide a packet synchronization detector that achieves a fast lock time to the synchronization byte position as well as to provide a method to operate such a packet synchronization detector.
These objects are achieved by a packet synchronization detector according to claim 1 and a method to determine the lock-in to a regularly repeated predetermined synchronization pattern within an incoming digital signal according to independent claim 7. Preferred embodiments thereof are respectively defined in the respective dependent claims.
According to the present invention a packet synchronization detector comprises a synchronization pattern detector that outputs a control signal whenever the incoming digital signal carries the predetermined synchronization pattern and several parallel synchronization state machines which respectively pursue their own synchronization byte location until lock has been obtained. The lock-in of the system is achieved when the first of those synchronization state machines has locked. Therefore, according to the present invention the time to lock is minimized in case there are as many synchronization state machines as synchronization bytes are detected within one transmission packet or frame, e. g. one MPEG transport packet. A preferred number of synchronization state machines is 16.
This preferred number of 16 synchronization state machines results from the observation that within one DVB transport packet an average of 13 . . . 14 synchronization byte patterns (0xc3x9747, 0xc3x97b8) is present and that on average 80% of the packets contain 16 or less synchronization byte patterns, whereas 35 synchronization patterns per 204-byte packet seem never to be exceeded.